The present invention relates to an amplifying solid-state image pickup device.
Conventionally, there has been proposed an amplifying solid-state image pickup device which has a pixel section having an amplification function and a scanning circuit disposed around the pixel section, where pixel data is read from the pixel section by the scanning circuit. In particular, there has been known an APS (Active Pixel Sensor) type image sensor formed of CMOSs (Complementary Metal Oxide Semiconductor) which are advantageous for integration of the pixel part with peripheral drive circuit and signal processing circuit.
For the APS type image sensor, there is a need for forming a photoelectric conversion part, an amplification part, and a pixel select part and a reset part normally within one pixel. Therefore, in the APS type image sensor, normally, three to four MOS transistors (Tr) are used in addition to the photoelectric conversion part formed of photodiodes (PD).
FIG. 8 shows a construction of an APS type image sensor which employs one photodiode (PD) and four MOS transistors (Tr) to make up a PD+4Tr system. This PD+4Tr system APS image sensor is disclosed in, for example, Reference “I. Inoue et al., IEDM Tech. Digest, pp. 883–886 (1999).”
The APS type image sensor of the PD+4Tr system shown in FIG. 8 is made up of a photodiode 201 as a “PD” and, as the “4Tr,” a transfer transistor 202 for transferring signal charge stored in the photodiode 201, a reset transistor 231, an amplification transistor 232 and a pixel select transistor 233. In this case, assuming that the photodiode 201 is given as buried type and signal charge transfer from the photodiode 201 is perfect, it is known that quite great noise reduction can be achieved and that high-quality images can be obtained.
A drive pulse for the transfer transistor 202 is represented by φT, a drive pulse for the reset transistor 231 is represented by φRR, and a drive pulse for the pixel select transistor 233 is represented by φS. Also, a vertical signal line 235 is grounded via a constant-current load transistor 234 to which a drive pulse φL is applied, where an output signal VS is obtained. In addition, VDD represents a power supply voltage (constant voltage).
For the amplifying solid-state image pickup device, it is useful to obtain a high resolution by reading out all the pixels independently of one another in the still picture mode and to enhance a read frame speed or sensitivity despite sacrificing the resolution by performing addition among pixels in the moving picture mode.
However, in the case of the amplifying solid-state image pickup device shown in FIG. 8, there would arise a problem as follows. That is, because signal charge is converted and amplified into a voltage signal and then read out from pixel to pixel, the addition operation among pixels is one to be performed among the read voltage signals. This require analog or digital memory elements in addition to the pixel section for the purpose of the addition operation, resulting in a more complex read circuit construction. Further, this method is poor in the S/N (Signal-to-Noise ratio) improvement effect. The reason of this is as follows.
Here is examined an addition between two pixels P1 and P2. Signals at the pixels are assumed as s1 and s2, respectively, and noise generated at the photoelectric conversion part is assumed as np1 and np2, and noise generated at the in-pixel amplification part is assumed as na1 and na2. Since noise np1 and np2 and noise na1 and na2 are not mutually correlated but independent of each other, total noise n12 is as shown by the following equation (Eq. 1):n12=√{square root over (()}np12+np22+na12+na22)  (Eq. 1)
A total signal s12 is as shown by the following equation (Eq. 2):s12=s1+s2  (Eq. 2)
Assuming a case where noise generated at the photoelectric conversion part is suppressed so that (np1, np2)<<(na1, na2) and where signals P1 and P2 are of the same and generated noise is also equivalent,s12=2·s1 and n12=√{square root over (2)}·na1,s12/n12=√{square root over (2)}·(s1/na1)  (Eq. 3)so that the S/N is improved only to √{square root over (2)} times.
Here is examined a case where the addition operation between pixels is performed before the conversion to voltage and the amplification, and then a signal after the addition is read out.
In this case, the noise after the addition is represented by the following equation (Eq. 4), being smaller than that of (Eq. 1):n12=√{square root over (()}np12+np22+na12)  (Eq. 4)
On the other hand, since the signal is represented by (Eq. 2) through charge addition, a case is examined in which (np1, np2)<<(na1) and the signals P1 and P2 are of the same.Since s12=2·s1 and n12=na1,s12/n12=2·(s1/na1)  (Eq. 5)so that the S/N is improved to two times. An example of this operation is shown below.
FIG. 9 shows an amplifying solid-state image pickup device in which a signal charge storage part 208, a reset transistor 231, an amplification transistor 232 and a pixel select transistor 233 are provided in common to a plurality of photodiodes 201 and transfer transistors 202 (see, e.g., JP 09-46596 A).
In FIG. 9, the same symbols as those in FIG. 8 represent the same contents as those in FIG. 8. FIG. 9 differs from FIG. 8 in that one set of a charge detection part 208, a reset transistor 231, an amplification transistor 232 and a pixel select transistor are provided in common to upper-and-lower two pixels. As a result, turning ON simultaneously a drive pulse φT(m, 1) of a transfer transistor 202 of a pixel (m, 1) and a drive pulse φT(m, 2) of a transistor of a pixel (m, 2) makes it possible to read out added-up signal charge of photodiodes 201 of the upper-and-lower two pixels (m: natural number).
However, in the construction and operation of the amplifying solid-state image pickup devices shown in FIG. 9, there arise problems as shown below. That is, given that the capacity of the common signal charge storage part 208 is CFD, a charge-voltage conversion efficiency η at which signal charge Qsig derived from the photodiode 201 is converted to a voltage signal Vsig isη=GSF·Vsig/Qsig=GSF/CFD  (Eq. 6)where GSF is the gain of a source follower circuit made up of the amplification transistor 232 and the constant-current load transistor 234, being smaller than 1.
As apparent from Equation 6, the capacity CFD needs to be reduced in order to enlarge the charge-voltage conversion efficiency η. The capacity CFD of the common signal charge storage part 208 is a sum of a drain-side junction capacitance of the transfer transistor 202 and a gate capacitance of the amplification transistor 232, both transistors being connected to the signal charge storage part 208. Therefore, the drain junction capacitance of the transfer transistors and wiring capacitance increase according as the number of photodiodes and transfer transistors connected to a common signal charge storage part increases, which leads to a problem that the charge-voltage conversion efficiency η decreases.